The present invention relates to a phase-locked loop (PLL) and, more particularly to a digital PLL having enhanced phase error compensating circuit to control sourcing and/or sinking current of the digital PLL.
A digital PLL generally produces output pulse stream or output clock pulses of which frequencies are related to a reference input frequency. A digital PLL requires a digital phase comparator which produces a direct current (DC) output in proportion to a phase difference between, for example, output clock pulses and reference clock input pulses. The DC output is used to control a frequency of a voltage-controlled oscillator (VCO) of the digital PLL, which generates the output clock pulses. Typically, the phase comparator is combined with a charge pump that acts to set a voltage developed across a loop filter capacitor. When current is pumped into a loop filter capacitor, DC voltage across the capacitor increases. On the contrary, when current is pumped out, the DC voltage decreases. The loop filter capacitor is connected to the VCO to set its frequency.
Such an arrangement, however, has a dead band range in which the VCO changes phase without producing sufficient phase comparator output to activate the up/down charging mechanism of the charge pump. Thus, the VCO dithers within the dead band, and this reduces spectral purity of the VCO output (or oscillator signal).
One way to avoid such a dead band is set forth in AN ECL/I2L FREQUENCY SYNTHESIZER FOR AM/FM RADIO WITH AN ALIVE ZONE PHASE COMPARATOR, by Donald R. Preslar and Joseph F. Siwinski, at pages 220-226, IEEE Transactions on Consumer Electronics (August of 1981). This publication shows a conventional digital phase comparator in which a delay element is incorporated in a reset circuit. This results in both up and down charge pumps being xe2x80x9conxe2x80x9d for a zero phase error. Such an action ensures that there is no appreciable dead band, so that the comparator has been called an alive zone comparator.
A main problem of the alive zone comparator, however, is that delay time by the delay element must be longer than turn-on time of the charge pump. This time is determined by such variables as temperature, fabrication process, and charge pump output voltage. Accordingly, the delay is normally made longer than the worst case turn on time and this renders the period of time, during which both charge and discharge currents are xe2x80x9conxe2x80x9d, excessive. This can lead to a phase error when the charge and discharge currents are not exactly equal.
FIG. 1 shows a block diagram of a conventional digital PLL. Terminal 10 provides a stable source of signal as a reference input fi. For example, a crystal controlled oscillator is coupled to the terminal 10, and a frequency divider (not shown) can be interposed therebetween. A phase comparator 11 compares the reference input fi with a feedback signal on line 12 to produce an output on either line 13 which directs a charge pump 15 to source current or line 14 which directs the charge pump 15 to sink current. A capacitor 16 schematically represents a low pass filter which supplies a control voltage to a VCO 17. The PLL 1 generates output signal fo of the VCO 17 through an output terminal 18. A frequency divider 19 is programmed by a digital control word signal 20 determining a division ratio N. Thus, the signal on line 12 is fo/N. The PLL will adjust the VCO 17 until the two inputs to the phase comparator 11 are in phase. A use of the programmable frequency divider 19 enables the PLL to perform a digital control, via the digital control word signal 20, of a frequency of the output signal fo at the terminal 18.
In a conventional digital PLL with a conventional phase comparator, however, there is a dead band at which the VCO output dithers. This results in a low purity spectrum of the output signal fo. To improve the purity spectrum of the output signal fo, thus, a delay element can be used. See IEEE Publication, Preslar and Siwinski, at pp. 220-226. FIG. 2 shows a typical phase comparator with a delay element. A delay element 21 is added to turn off NAND gate 22 which is activated by means of NAND gates 23-28 connected to drive NAND gates 29 and 30. Terminal 31 supplied with a reference input fi is coupled to an input of NAND gate 23, and terminal 32 supplied with a feedback input fb coupled to an input of NAND gate 28. The gate 29 and the gate 30 provide a up control signal UP and a down control signal DOWN to the charge pump, respectively. The delay element 21, which typically comprises four cascaded inverter gates, provides a signal delay between a reset gate 22 and output control gates 29 and 30. The amount of delay of delay element 21 should be adequate to ensure that the charge pump 15 conducts for sourcing and sinking current from filter 16 for an interval after the phase comparator 11 resets. As mentioned above, such a delay is made to exceed a maximum value that the conventional digital PLL needs.
It is an object of the present invention to provide a digital phase-locked loop circuit with reduced power consumption during a phase error compensating operation.
It is another object of the present invention to provide a digital PLL circuit having a zero dead zone.
To attain the above objects, a digital PLL circuit of the present invention provides a wide range of output frequencies in response to an input signal having an input frequency. The circuit comprises a VCO for producing an output signal having an output frequency in response to a control voltage provided from a loop filter, a frequency divider for dividing the output frequency of the output signal by a divisor to produce a divided output signal having a divided output frequency, and a sensing circuit for preventing a needless delay time of a charge pump.
The present invention will be better understood from the following detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.